This invention is generally related to the fabrication of a three-dimensional integrated circuit (IC) chip or wafer assembly, and more particularly to a method of stacking ultra-thin chips with interconnections designed to maximize the speed of the overall IC package.
Three-dimensional integrated circuits (3D-IC) have proven to be the favored approach for improving the performance of semiconductor products. Density can be upgraded many fold by stacking chips or wafers. Significant speed improvement can also be expected because the interconnecting wires linking the chips are shortened substantially.
Several techniques for achieving 3D-IC configurations have been used in the past. One approach utilizes a fabrication technology wherein active silicon films are grown in successive layers with intervening insulation layers. However, this approach must overcome many problems related to the materials used. Furthermore, the processes involved in forming successively devices can affect the characteristics of devices placed underneath it. In addition, the total fabrication time and complexity is proportional to the number of layers, and becomes impractical for higher levels of 3D integration. A typical technique of forming a 3D-IC assembly by stacking silicon-on-insulator (SOI) wafers, but using a temporary silicon substrate, is described, e.g., in U.S. Pat. No. 5,426,072 to Finnila. are several problems associated with stacking wafers. First, the yield loss is very large. Assuming a typical 70% yield for each finished wafer, by stacking two wafers, the maximum yield achievable is 49%, (i.e., 0.7xc3x970.7), assuming no yield loss in the stacking process. A low yield forcibly results in a significant increase in cost. The second problem is related to alignment. Nowadays, almost all lithographic processes use optical steppers. The stepper only aligns and exposes one die at a time. Thus, images in different die areas do not aligned, as a result of which it is a common occurrence that the two wafers end up misaligned. To solve this problem, the feature size of the interconnect required for stacking needs to be very large which, in turn, degrades the density and performance of the 3D-IC.
Since the chips in each wafer are tested to screen out defective ones, one must stack only good chips on top of good chips on a wafer to maintain a reasonable yield. If there is no yield loss during the stacking process, the final yield will coincide with the original wafer yield. In as much as one or more chips need to be aligned at any one time, the alignment tolerance is significantly superior than stacking wafers on top of one another. Hence, stacking chips is definitely the preferred approach for attaining 3D-IC.
In order to achieve the desired results, optical alignment has been used extensively in today IC technology. Optical alignment can be used as long as the alignment marks on both dies are visible. This is feasible, as will be explained hereinafter. Alternatively, an electrical alignment can be utilized, although it requires additional circuitry to realize this alignment. A distinct advantage resides in the ability of this optical technique to align with tolerances close to the minimum feature size of the technology. Lastly, to extend 3D-IC to as many layers as possible, metal must be present in the topmost and lowermost layer of the wafer. As described below, it is much easier to fabricate fine metal patterns on the bottomside of the wafer using SOI technology than bulk technology. It is also extremely difficult to achieve very thin stacking chip ( less than 10 micron) using bulk CMOS technology.
In order to better understand the structure of the present invention, a description of the steps to prepare a wafer to form the structure of the present invention will be described next with reference to FIG. 1a to FIG. 1e. Details of such construction may be found in U.S. patent application Ser. No. 09/481,914, filed on Jan. 12, 2000, and incorporated herein by reference. Therein, an SOI wafer consisting of an SOI silicon substrate (100), a buried oxide layer (BOX) (140), an SOI film (150) and multi-layer metal (130) above the SOI is shown in FIG. 1a. Active and passive device components are built on the SOI above the BOX. The wafer can be fabricated using CMOS technology, bipolar technology, GaAs technology, optical devices or any other technology. The buried oxide (140) and the bulk-Si substrate (100) can be replaced with other dielectric material as long as one can remove the thick substrate and stop exactly on the buried dielectric. An optional metal layer below the BOX may be needed to minimize the resistance of the interconnections between stacked chips. Next, a handling wafer (170) is attached at the topmost layer of the wafer (210), as shown in FIG. 1b. This handler is preferably made of silicon or glass, having a thickness adequate for mechanical handling (e.g., for an 8 inch wafer, the thickness is in the order of 0.5mm ). The handler has preferably the same shape as the wafer and has its edges aligned with the wafer edges. Glue (160) which is utilized must withstand temperatures of up to around 400xc2x0 C. because of the later buried metallization process. The handling substrate consists of bulk material, SOI or glass, although glass is preferable because of its transparency, and further, it makes it possible to use optical alignment to stack the chips. The glue is preferably also made of a transparent material as well. For the purpose of chip stacking, it is preferable to remove the handler after each stacking process. As a result, the glue material has to be chosen such that it can facilitate the handler removal process and expose the upper metal layer. One way of accomplishing this is by using polyimide as the glue material. A laser beam passing through the glass can be focused on the polyimide, locally melting it and allowing the handling substrate to be removed with ease.
In FIG. 1c, the bulk silicon (100) is removed by a chemical and/or mechanical grinding process until the buried oxide (BOX) (140) is exposed. Such etch back process is similar to the one developed for bond-and-etch-back SOI process, known in the art, except that now the chemical etch, usually KOH, a potassium-hydroxide solution, conveniently stops at the buried oxide. This results in a perfectly flat and clean oxide surface. The chemical etching must be the last etching step because the mechanical grinding does not stop on oxide. The high quality buried oxide (BOX) is critical in the formation of such flat and clean oxide surface at the bottom. This surface is essential for allowing the usage of high resolution lithography to maximize the number of feedthroughs from the top-side and bottom-side of the chip. The perfect chemical etch stop also allows the stacking chip to be extremely thin (less than 10 micron). Without the BOX layer (in case of bulk technology), a timing etching or grinding process can be used. However, the bottom surface is rough and the stacking chip significantly thick (100 microns and above). Therefore, it is important to emphasize that the present invention employs SOI material as well as an innovative processing technique to achieve ultra-thin stacking chip as well as maximizing the number of interconnections between the stacked chips.
In FIG. 1d, a standard lithography process opens the via for etching. The via is aligned to the front side pattern of the original wafer. The buried oxide is typically 100-300nm, making it for all practical purposes transparent. The via mask is mirrored for proper alignment. The oxide in the opening area is then removed using an etching technique, such as RIE. The via opening (165) is then filled with suitable plug material, preferably metal, such as tungsten. If the opening is sufficiently wide, metal (aluminum or copper) can be formed by a single damascene process. In FIG. 1e, multilayer metal (190) (preferably, Cu or Al) is formed below of the BOX (140) by conventional metal deposition and etching. These metal layers interconnect the vias positioned in the BOX layer. The last metal layer is provided with an appropriate structure for proper chip attachment, which will be discussed in more detail hereinafter. For ease of discussion, the multilayer metal (130) described above the SOI is assumed to be the topmost layer to be used for metal routing, whereas the multilayer metal below (190) the BOX is assumed to be the bottommost layer providing metal routing.
Accordingly, it is an object of the invention to fabricate a 3D-IC structure by stacking chips on a wafer or a chip on top of another chip.
It is another object of the invention to use an SOI buried metal process to provide interconnections at the substrate interface to allow a continuous stacking of any number of chips.
It is a further object of the invention to stack the chips while maintaining a precise alignment between all the chips forming the stack.
It is yet another object of the invention to stack chips one on top of another while maintaining good mechanical and thermal integrity.
The objects of the invention are realized by providing a method of fabricating a three-dimensional integrated circuit (IC) assembly, the assembly being formed by a plurality of individual SOI chips, each of the SOI chips including: a handler making mechanical contact to a first metallization pattern, the first metallization pattern making an electrical contact to a semiconductor device, the semiconductor device making electrical connect to a second metallization pattern positioned on an opposite surface of the semiconductor device, the method of fabricating the three-dimensional IC assembly including the steps of: a) providing a substrate having a third metalized pattern on a first surface of the substrate; b) aligning one of the S0I chips on the first surface of the substrate by having the second metallization pattern of the SOI chip make electrical contact with the third metalized pattern of the substrate; c) removing the handler from the SOI chip, exposing the first metallization pattern of the SOI chip; d) aligning a second one of the SOI chips with the first SOI chip and having the second metallization pattern of the second SOI chip make electrical contact to the exposed first metallization pattern of the first SOI chip; and e) repeating steps c) and d) for mounting subsequent SOI chips one on top of another.
In another aspect of the invention, there is provided a three-dimensional integrated circuit (IC) assembly, the assembly formed by a plurality of individual SOI chips, each of the SOI chips comprising a handler making mechanical contact to a first metallization pattern, the first metallization pattern making an electrical contact to a semiconductor device, the semiconductor device making an electrical connect to a second metallization pattern positioned on an opposite surface of the semiconductor device, the three-dimensional IC assembly including: a) a substrate having a third metalized pattern on a first surface of the substrate; b) a first plurality of SOI chips positioned on the first surface of the substrate with the second metallization pattern of the SOI chip making electrical contact with the third metalized pattern of the substrate; c) with the handler removed from the SOI chip and with the first metallization pattern of the SOI chip exposed, a second plurality of the SOI chips aligned with the first plurality of SOI chips, wherein the second metallization pattern of the second SOI chip makes electrical contact with the exposed first metallization pattern of the first SOI chip; and d) subsequent levels of aligned SOI chips, each of the levels of SOI chips being placed and aligned on top of a previous level of the SOI chips until a predetermined height of the stack of SOI chips is reached.
In summary, there is disclosed a three-dimensional integrated circuit (3D-IC) assembly consisting of a plurality of wafers stacked one on top of the other. This assembly further extends to include stacking chips on a wafer or chips on top of another chip on top of any type of substrate, card, interposer, and the like. Finally, an SOI buried metal process is described that provides the necessary interconnections at the substrate interface, making it possible to successively stack any number of chips. In order to properly stack all the chips as described, a precise alignment between all the chips forming the stack is required to maintain good mechanical and thermal integrity.